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Lattice Semiconductor
PCI Express User’s Guide
Introduction
PCI Express is a high performance, general purpose Serial I/O Interconnect de?ned for a wide variety of future
computing and communication platforms. The basic premise of PCI Express is that the host PCI software remains
compatible with an endpoint device without new drivers or operating-system software. Salient PCI attributes, such
as its usage model, load-store architecture, and software interfaces, are maintained, whereas its bandwidth-limiting
and parallel bus implementation is replaced by a highly scalable, fully serial interface. PCI Express takes advan-
tage of recent advances in point-to-point interconnects, switch-based technology, and packetized protocol to
deliver new levels of performance and features.
Lattice’s PCI Express IP Core is an endpoint device supporting a x1 link. It consists of three layers of the endpoint
device namely the Physical, Data Link and Transaction layers. This IP core targets the programmable array of the
ORCA Series 4 ORT42G5 FPSC. The complete solution supports up to 2.5Gbps data rate as speci?ed in PCI
Express Speci?cation 1.0a . For more information on this and other Lattice products, refer to the Lattice web site at
www.latticesemi.com.
This user’s guide explains the functionality of the Lattice PCI Express core and how it can be implemented to pro-
vide endpoint interface to an application running in the Transaction layer.
The PCI Express core comes with the following documentation and ?les:
? Data Sheet
? User’s Guide
? Lattice gate level netlist
? Model for simulation
? Core instantiation template
? Testbench and testbench coding template
Features
? Lane width of x1 con?guration.
? Effective raw data rate of 2.5Gbps/lane/direction (with target device support).
? 8b/10b encoding / decoding for symbols and special symbols (with target device support).
? Data scrambling / de-scrambling
? Link initialization and training.
? Flow control initialization.
? Data integrity checking for both Data Link Layer Packets and Transaction Layer Packets.
? Data Link Layer retry mechanism for transmitted Transaction Layer Packets.
? Acknowledgement and Timeout replay mechanisms.
? All error statuses are reported in the backend User Interface
? Credit availability calculation and reporting
General Description
PCI Express ties together various components within a system and provides connection points for future high-
speed devices. The following diagram gives an overview of how PCI Express is used in a typical system.
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